Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture  

作　　者：WANG YanSheng LIU LeiBo YIN ShouYi ZHU Min CAO Peng YANG Jun WEI ShaoJun 

机构地区：[1]Institute of Microelectronics, Tsinghua University [2]National Laboratory for Information Science and Technology, Tsinghua University [3]National ASIC System Engineering Technology Research Center, Southeast University

出　　处：《Science China(Information Sciences)》2013年第11期275-294,共20页中国科学（信息科学）（英文版）

基　　金：supported by National Natural Science Foundation of China(Grant No.60803018);National High-tech R&D Program of China(863 Program)(Grant No.2009AA011702)

摘　　要：In reconfigurable system, fast reconfiguration and small size of configuration contexts are strongly required to enhance the processing performance and reduce the implementation overhead. In this paper, a hierarchical representation of contexts for CGRA called HCC is proposed to satisfy the above requirements. In HCC, the contexts are constructed in a hierarchical fashion to thoroughly eliminate the repetitive portions of the contexts, not only reducing the overall contexts storage size, but also alleviating the contexts transportation overhead. The fast context-indexing mechanism is proposed in HCC to achieve high configuration speed, since the hierarchically organized contexts can be located and accessed conveniently. HCC has been verified in a reconfigurable processor called REMUS_HP. Owing to HCC, when implementing H.264 decoding on REMUS_HP, 76.67% of the overall contexts are reduced compared with the traditional non-hierarchical one; and the configuration speed is averagely 23× increased compared with the latest reported optimized configuration mechanism on Virtex-4 FX60. REMUS_HP is implemented on a 48.9 mm^2 silicon with TSMC 65 nm technology. Simulation shows that 1920 ×1088@30 fps could be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP, the performance is 181% boosted.In reconfigurable system, fast reconfiguration and small size of configuration contexts are strongly required to enhance the processing performance and reduce the implementation overhead. In this paper, a hierarchical representation of contexts for CGRA called HCC is proposed to satisfy the above requirements. In HCC, the contexts are constructed in a hierarchical fashion to thoroughly eliminate the repetitive portions of the contexts, not only reducing the overall contexts storage size, but also alleviating the contexts transportation overhead. The fast context-indexing mechanism is proposed in HCC to achieve high configuration speed, since the hierarchically organized contexts can be located and accessed conveniently. HCC has been verified in a reconfigurable processor called REMUS_HP. Owing to HCC, when implementing H.264 decoding on REMUS_HP, 76.67% of the overall contexts are reduced compared with the traditional non-hierarchical one; and the configuration speed is averagely 23× increased compared with the latest reported optimized configuration mechanism on Virtex-4 FX60. REMUS_HP is implemented on a 48.9 mm^2 silicon with TSMC 65 nm technology. Simulation shows that 1920 ×1088@30 fps could be achieved for H.264 high-profile decoding when exploiting a 200 MHz working frequency. Compared with the high performance version of XPP, the performance is 181% boosted.

关 键 词：reconfigurable computing hierarchical configuration context REMUS_HP fast reconfiguration context compression 

分 类 号：TN406[电子电信—微电子学与固体电子学]