A Temporal Locality-Aware Page-Mapped Flash Translation Layer  

作　　者：Youngjae Kim Aayush Gupta Bhuvan Urgaonkar 

机构地区：[1]National Center for Computational Sciences,Oak Ridge National Laboratory [2]IBM Almaden Research Center [3]ACM [4]IEEE [5]Department of Computer Science and Engineering,Pennsylvania State University,University Park

出　　处：《Journal of Computer Science & Technology》2013年第6期1025-1044,共20页计算机科学技术学报（英文版）

基　　金：funded in part by the Natural Science Foundation of U.S.under Grant Nos.CCF-0811670,CNS-0720456;a gift from Cisco System,Inc.and partially through the Ofce of Science of the U.S.Department of Energy under Contract No.DE-AC05-00OR22725

摘　　要：The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance： the design of the flash translation layer （FTL） which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer （DFTL） which selectively caches page- level address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating： 1） improved performance, 2） reduced garbage collection overhead and 3） better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time （due to a 3-fold reduction in operations of the garbage collector）, compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance： the design of the flash translation layer （FTL） which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer （DFTL） which selectively caches page- level address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating： 1） improved performance, 2） reduced garbage collection overhead and 3） better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time （due to a 3-fold reduction in operations of the garbage collector）, compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.

关 键 词：flash memory flash translation layer storage system 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]