基于FPGA的扩频同步捕捉跟踪设计  

Spectrum synchronization design of capture and track based on FPGA

作　　者：李翔[1] 魏幼平[1] 李忠敏[1] 张衎[1] 韩国梁[1] 

机构地区：[1]中国矿业大学(北京)机电与信息工程学院,北京100083

出　　处：《微型机与应用》2013年第16期68-70,共3页Microcomputer & Its Applications

摘　　要：在扩频通信中,接收端的参考伪随机序列码是否与接收的扩频码同步是能否正确解扩的关键。对伪随机序列同步原理、同步捕获正误、同步判决门限值及解扩时的竞争冒险进行了分析及方案设计;通过边沿捕捉、伪随机码自相关函数处理、虚警看门狗闭环模块协同作用,实现扩频码的精确同步与解扩。系统设计采用QuartusII、DSPBuilder与Simulink联合开发平台,可使用HDL语言设计创建IP,即时查看设计仿真结果,快速进行工程设计。In communications of spreading spectrum, the receiving end of the reference pseudo-random sequence code with the received spread code synchronization is the key to whether its correct despreading. The article describes that the analysis and the program design that included the principle of a pseudo-random sequence synchronization, synchronous capturing of right and wrong, synchronization decision threshold and despreading competitive adventure; By edge capturing, the processing of the code of autocorre- lation function of pseudo-random, the closed-loop module of watchdog of false alarm which synergy the precise role in achieving the spreading code synchronization and despreading. System design using tools include QuartuslI, DSP Builder and Simulink joint development platform . HDL language can designs created IP, and desiners can look at the design simulation results in time, and make engineering fast.

关 键 词：扩频 同步捕捉 伪随机码 

分 类 号：G644[文化科学—高等教育学]