基于变长切换的多数据流正则表达式匹配  

Variable length switching based multi-stream regular express matching

作　　者：贺炜[1] 郭云飞[1] 莫涵[1] 扈红超[1] 

机构地区：[1]国家数字交换系统工程技术研究中心,河南郑州450002

出　　处：《计算机工程与设计》2013年第11期3856-3861,共6页Computer Engineering and Design

基　　金：国家科技支撑计划基金项目(2012BAH02B03;2012BAH02B01);国家863高技术研究发展计划基金项目(2011AA01A103;2011AA01A101;2011BAH19B04)

摘　　要：为支持多条数据流的正则表达式匹配,提出一种基于FPGA的正则表达式匹配系统(VLS Memory-DFA)。通过具有记忆特性的DFA结构实现了匹配过程的灵活中断和恢复,通过变长切换机制保证了多条数据流处理的公平性和切换的快速性。通过部署于FPGA,该系统在3386条规则下,最大能够支持92条数据流的同时处理,能够达到236MHz的时钟频率以及7.55Gbps的吞吐率。处理结果表明,VLS Memory-DFA能够满足多数据流的处理需求,并达到较高的处理速率。Abstract. A new REM system variable length switching memory deterministic finite automata （VLS Memory-DFA） is proposed for multi-streams matching. VLS Memory-DFA based on FPGA consists of two key components： Memory-DFA and VLS mechanism is realized. Memory-DFA gives facilities for interruption and recovering in multi-stream matching process. VLS guaran tees the justice and fast switching among several streams. FPGA implementation show that VLS Memory-DFA can match 3386 regex rules against up to 92 concurrent streams with clock frequency 236MHz and throughput of 7.55Gbps. VLS Memory-DFA could meet the necessary of multi-stream and achieve high throughput.

关 键 词：多数据流 正则表达式匹配 变长切换 现场可编程门阵列 高速 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]