单双精度浮点加法的可重构设计研究  

Research on reconfigurable design of single-precision and double-precision floa-ting-point addition

作　　者：范继聪 洪琪[1] 

机构地区：[1]安徽大学电子信息工程学院,安徽合肥230601

出　　处：《计算机工程与设计》2013年第11期3889-3893,共5页Computer Engineering and Design

基　　金：专用集成电路与系统国家重点实验室开放课题基金项目(10KF014)

摘　　要：为了节约资源,提高浮点加法运算的灵活性,提出一种支持一个双精度浮点加法和两个并行的单精度浮点加法的可重构加法器结构。该加法器结构遵循IEEE754标准,可以实现在双精度浮点加法和单精度浮点加法之间的功能切换,实现资源重用。通过大量的测试验证,该结构功能完全正确。通过资源共用,可以避免资源闲置,综合结果显示该设计在比双精度浮点加法器多用23.5%面积的前提下,可以并行实现两个单精度浮点加法,比实现相同功能的一个双精度浮点加法器和两个单精度浮点加法器共节省40%左右的面积。To save resources and improve the flexibility of the floating-point adder, a reconfigurable floating-point adder structure which is support a double-precision floa-ting-point addition and two parallel single-precision floating-point addition is proposed. This adder architecture is compliant to the IEEE754 standard and can support the function switch between single precision floating-point addition and double precision floating-point addition, so the resource reuse is achieved. The correctness of this architecture is tested and verified through extensive simulation. This structure can avoid idle resources through sharing resources, the synthesizing results show that this design on premise of using 23.5 % area more than the double-precision floating-point adder, can executes two single-precision floating-point addition in parallel, and also can save about 40% area than the same functionality achieved by a double-precision floating-point adder and two single-precision floating-point adder.

关 键 词：浮点算术运算 可重构设计 IEEE754标准 功能切换 资源重用 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]