基于边界控制的安全SoC芯片硬件结构设计  

Design of hardware architecture for secure SoC based on border control

作　　者：赵峰[1] 徐进辉[1] 戴紫彬[1] 何道君[2] 

机构地区：[1]解放军信息工程大学,河南郑州450000 [2]北方信息技术研究所,北京100072

出　　处：《电子技术应用》2013年第11期13-16,共4页Application of Electronic Technique

摘　　要：为满足大批量数据处理和信息安全的需要,基于通用处理器与专用密码协处理器设计了一款异构多核安全SoC芯片。在分析了高性能SoC主要结构和安全问题的基础上,融合安全硬件结构及边界控制思想,设计了密码服务区和应用开发区分离的多层安全SoC芯片硬件架构。对比不同权限电路设计方案后,采用真值表方法设计专用安全控制单元来实现两个区域的硬件隔离,并根据SoC芯片受到的安全威胁设定安全拦截规则。采用EDA工具进行仿真实验,结果表明安全控制单元能够有效拦截应用开发区对密码服务区的非法访问,保护芯片的安全而且产生的延迟较小。To meet the demand of the mass data processing and information security, the heterogeneous multi-core SoC chip including the general RISC processor and the dedicated cryptographic coprocessor is designed. Analyzing the structure of the perfor- mance SoC and fusing security hardware structure and security border control theory, this paper puts forward the multi-layered se- curity architecture of SoC, which has the application service area and the cryptographic service area. After comparing the different design scheme of authority circuit, the security control unit is designed using truth table method to realize two regions hardware iso- lation. Set security blocking rules according to the security threats for SoC chip. The simulation results show that the safety control unit can effectively intercept the application service area illegally accessing the cryptographic service area, and can protect data se- curity and has a low latency.

关 键 词：异构多核 片上总线 硬件隔离 密码服务区 安全边界控制 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]