新型适应性路由器微体系结构研究  

A novel adaptive router microarchitecture

作　　者：肖灿文[1] 戴泽福[1] 张民选[1] 

机构地区：[1]国防科学技术大学计算机学院,湖南长沙410073

出　　处：《计算机工程与科学》2013年第11期22-26,共5页Computer Engineering & Science

基　　金：国家863计划资助项目(2012AA01A301;2013AA014301)

摘　　要：路由器芯片是互连网络的核心部件。介绍一种支持完全适应性维度气泡路由的新型路由器微体系结构。针对维度气泡完全适应性路由算法的特点,优化设计了路由器的输入缓冲以及仲裁开关逻辑。采用DC工具评估了新型路由器的面积以及延迟。实验结果表明,相对基于Duato方法的适应性路由器芯片,新型路由器芯片更容易获得更高的主频。Router chip is a key component of interconnection network. A novel router microarchitec- ture is presented, which supports the fully adaptive Dimensional Bubble Routing Algorithm （DBRA）. According to the characteristics of DBRA, the design of input buffer, arbiter and switch of router is op- timized. The area and delay of router chip is evaluated by Design Compiler under the process of TSMC 40nm. The results show that the novel router chip is easier to achieve the higher frequency compared with the router chip based on Dauto＇s methodology.

关 键 词：路由器芯片 完全适应性维度气泡路由算法 输入缓冲 仲裁开关 Duato方法 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]