基于硬件事件的并行程序指令级性能模型与应用  

An instruction level performance model of parallel program based on hardware events

作　　者：罗红兵[1] 武林平[1] 

机构地区：[1]北京应用物理与计算数学研究所高性能计算中心,北京100094

出　　处：《计算机工程与科学》2013年第11期175-181,共7页Computer Engineering & Science

基　　金：国家863计划资助项目(2012AA01A309)

摘　　要：当前,应用程序持续运行性能与高性能计算机峰值性能的差距有扩大的趋势,许多实际应用程序的性能通常只能达到机器峰值性能的5％～10％,甚至更低,如何优化并行应用成为高性能计算领域关注的焦点.从如何利用硬件事件进行程序指令级优化入手,提出一种基于硬件事件的性能模型,揭示出程序性能与程序特征、微处理器特征的关系.基于该性能模型,在Intel Xeon微处理器平台上对Euler等程序进行优化,gas1dapproxy等性能热点模块的执行时间可以缩短12％～61％.性能优化实验表明：使用该性能模型可以降低用户进行指令级并行性能优化的难度,指导用户选择正确的性能优化方向.The gap between peak performance of supercomputer and sustained performance of appli- cations is becoming bigger and bigger, and many actual applications only reach 5%-10% of peak per- formance for supercomputer, or even less, therefore, performance problem is being gotten more and more concerns during parallel program development. A performance model based on hardware monitor events is proposed, which reveals relationship between performance and feature of program and proces- sor. Based on the performance model, Euler and other programs are optimized on the Intel Xeon plat- form, and the execution time of hotspot modules such as gasldapproxy is shortened by 12%-61%. The experiment results show that this model is helpful to optimize ILP performance of the scientific compu- ting applications.

关 键 词：性能分析 性能优化 性能模型 指令级并行 

分 类 号：TP302[自动化与计算机技术—计算机系统结构] TP38[自动化与计算机技术—计算机科学与技术]