基于H.264编码器的DDR3控制器设计  

Design of DDR3 Controller Based on H. 264 Encoder

作　　者：王林林[1] 郭勇[1] 袁兴[1] 李磊[1] 王桂海[1] 

机构地区：[1]山东科技大学信息科学与工程学院,山东青岛266590

出　　处：《电视技术》2013年第23期89-92,共4页Video Engineering

摘　　要：在分析H.264编码过程中对存储器带宽需求的基础上,设计了一种高效、通用的DDR3控制器。结合H.264编码器IP核与外存之间的地址映射关系和DDR3双倍速率传输的特性,采用减少DDR3的行、列切换及设计异步控制逻辑单元等方法缩减H.264编码器对外存的读写操作时间。该结构可使DDR3运行在比编码器更高的频率上,并保证跨时钟域间的数据同步,进一步提高外部存储器的带宽利用率。整个系统通过EDA工具进行仿真调试,并在Altera公司Stratix IV系列FPGA开发板上进行验证。An efficient and universal DDR3 controller is designed based on the analysis of the requirements of bandwidth during the H. 264 encoding process. Considering the address mapping between H. 264 encoder and peripheral memory ,also the double rate characteristic of DDR3, several methods are adopted todecrease the reading and writing time of external memory by H. 264 encoder, such as,reduction of rows and columns switching,designing asynchronous control logic unit. The structure allows DDR3 running on a higher frequency than the encoderand guarantee data synchronization which further improved external memory bandwidth utilization. The system is simulated and debugged by EDA tools and verified by the Stratix IV FPGA development beard of Altera Corporation.

关 键 词：H 264 DDR3 FPGA 异步传输 带宽 

分 类 号：TN919.81[电子电信—通信与信息系统]