基于FPGA的SATA Ⅱ主机端IP核设计  

Design of SATA ⅡHost Controller IP Core Based on FPGA

作　　者：朱佳齐[1] 陈泉根[2] 吴威[3] 许晏[1] 

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621900 [2]中国工程物理研究院计算机应用研究所,四川绵阳621900 [3]中国科学院光电技术研究所,成都610000

出　　处：《计算机测量与控制》2013年第11期3047-3049,3052,共4页Computer Measurement &Control

摘　　要：按照SATAⅡ协议标准,基于Xilinx FPGA完成主机端IP核的设计;采用硬件描述语言对要实现的电路进行描述,主要完成主机端物理层、链路层和传输层的设计;设计的SATAⅡ主机控制器IP核具有较高的集成度、较低的成本以及使用方便等优点;在对各模块设计过程中,采用的功能仿真工具为Modelsim,以确保每个模块功能的正确性。功能仿真通过后使用在线逻辑分析仪Chipscope对设计进行在线调试;通过下载调试,设计的IP核正确运行,满足SATA协议规范要求。According to SATA Ⅱ interface protocol, The design of SATA Host Controller IP core based on Xilinx FPGA is given. The designed IP core includes physical layer, link layer and transport layer, which is realized by using hardware design language. The SATA Ⅱ host controller IP core is highly integrated, lower cost and ease of use. During the design of the IP core, the functional simulation of the modules are implemented by Modelsim. Then using the logic analyzer Chipscope pro to debug the design. At last, the controller is running correctly and meet the requirements of the SATA protocol specification by the plate test results.

关 键 词：SATAlI FPGA IP 硬件描述语言 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]