新型低压低功耗基准电压源  

New type of voltage reference with low voltage and low power

作　　者：杜永乾[1] 庄奕琪[1] 李小明[1] 井凯[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件重点实验室,陕西西安710071

出　　处：《华中科技大学学报（自然科学版）》2013年第11期114-117,共4页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：中央高校基本科研业务费专项基金资助项目(K50510250011)

摘　　要：设计了一种低压、低功耗基准电压源电路．该电路采用工作在亚阈区的MOSFET与传统PNP晶体管相结合的方式，使得电路的输出基准电压与MOSFET阈值无关，具有较低功耗和较高精度．同时，虚拟二极管连接的偏置结构的引入提高了环路增益，进而提高基准源的电源抑制比（PSRR）．采用SMIC0．18“m工艺平台，并完成版图设计以及仿真验证．当基准源输出电压为0．702V时，电源电压工作范围为0．9～3．0V，静态功耗仅为0．6gW，其温度系数为13．6肛V／℃，PSRR接近80dB．在不同工艺角下，该基准电路的输出基准电压最大偏差为9mV．A voltage references for portable electronic products was described. By combining the con- ventional PNP transistors with MOS transistors, the operating current was reduced to achieve the goal of low power. The MOS transistor was biased in the sub-threshold region. The output voltage refer- ence had no correlation with the threshold voltage of MOSFET. As a result, it had a much better ac- curacy, compared with traditional sub-threshold voltage reference. The proposed virtually diode-con- nected biasing scheme for MOS transistors increased the loop gain, thus reducing the power supply sensitivity. Consequently, the power supply rejection ratio （PSRR） increased. The circuit was de- signed in a SMIC 0.18 vm standard CMOS technology. The post-simulation results show a tempera- ture coefficient of 13.6 vV/~C. The power consumption is 0.6 ~W from a 0.9~3.0 V supply voltage, and the PSRR is 80 dB. The maximal absolute voltage variation at different process corners is 9 inV.

关 键 词：基准源 低压 低功耗 电源抑制比 亚阈区 

分 类 号：TN202[电子电信—物理电子学]