基于遗传算法的数字集成电路多故障测试生成方法  

Multi-fault Test Generation Method of Digital Integrated Circuit Based on Genetic Algorithm

作　　者：马长李[1] 马瑞萍[1] 廖剑[2] 

机构地区：[1]海军装备研究院,北京100161 [2]海军航空工程学院控制工程系,山东烟台264001

出　　处：《仪表技术》2013年第12期25-28,共4页Instrumentation Technology

摘　　要：在数字集成电路多故障测试生成算法的研究中,寻求具有高故障覆盖率,较短测试生成时间是问题的关键。文中采用遗传算法,通过对已有算法的分析,提出了计算简单、切实有效的适应度函数,减小了算法的时间复杂度,实验结果证明该算法可以有效地得到故障的测试矢量。Based on the research on Hopfield neural networks model, the multi-fault test generation algorithm of combinational circuits has been studied for the purpose of improving faults coverage and reducing the test generation time. Genetic algorithm was used. An easy and effective fitness function was proposed in this paper through analyzing ex- isting algorithms. It cuts down the algorithmic time complexity. The result shows that the proposed algorithm can gain the multi-fauh test vectors more effectively than others

关 键 词：数字集成电路 测试生成算法 HOPFIELD神经网络 遗传算法 

分 类 号：TP207.1[自动化与计算机技术—检测技术与自动化装置]