AES算法的FPGA实现与嵌入式系统应用测试  

FPGA implementation of AES algolithm and appucation testing in the embedded system

作　　者：薛小铃[1] 贾俊荣[1] 刘志群[1] 

机构地区：[1]闽江学院物理学与电子信息工程系,福建福州350121

出　　处：《闽江学院学报》2013年第5期62-65,共4页Journal of Minjiang University

基　　金：福建省教育厅科技项目(JB10129)

摘　　要：随着网络技术的不断发展以及智能化产品的深入应用,信息安全越来越受到人们的重视.基于FPGA设计并实现了AES算法,采用资源共享的方法设计加、解密模块,采用组合逻辑电路的方法设计S盒,减少了芯片面积,提高了加、解密速度.仿真与应用测试结果表明,该设计的AES算法具有占用资源少、速度较快、成本低等特点,在性价比上具有较大的优势,很适合应用于嵌入式系统中.With the development of internet technology and the deepening application of intelligent prod- uct, information security attracts more and more attention. This paper introduces the design and realization of AES algorithm based on FPGA. It designed the eneryption and decryption module by using the method of resource sharing and the S - box by using the combined logic circuit method, which reduced the chip area and improved the encryption and decryption speed. The results of simulation and application testing indicate, the design of the AES algorithm is characteristic of less resource, faster speed, low cost, high performance -price ratio, and it is suitable for application in the embedded system.

关 键 词：AES算法 FPGA 嵌入式系统 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]