应用于GFSK开环调制的幅度可编程DAC设计  

Design of Amplitude-Programmed DAC Applied for Open-Loop GFSK Modulator

作　　者：陈伟庆[1,3] 李富华[1] 阴亚东[2,3] 

机构地区：[1]苏州大学电子信息学院先进传感器与系统研究所,苏州215000 [2]中国科学院微电子研究所,北京100029 [3]中国科学院微电子研究所昆山分所,江苏昆山215347

出　　处：《半导体技术》2013年第12期899-904,共6页Semiconductor Technology

基　　金：国家科技重大专项03专项基金资助项目(2012ZX03004006)

摘　　要：采用中芯国际(SMIC)公司的0.18μm 1.8 V CMOS工艺设计实现了一款应用于高斯频移键控(GFSK)开环频率调制系统中的数模转换器(DAC)电路。为实现GFSK调制系数可编程,并有效降低DAC电路的功耗和芯片面积,该DAC的低7位数据位通过R-2R梯形结构的二进制加权电阻网络完成高速数模转换功能;同时高3位数据位通过逻辑译码电路调整R-2R梯形电路的偏置电压,实现DAC输出电压幅度的可编程,从而完成了GFSK调制系数的编程控制。芯片测试结果显示,在1.8 V电源电压供电下,当数据转换频率为16 MHz时,DAC能有效完成数模转换功能,消耗电流约为0.55 mA,并且DAC芯片版图面积小于0.02 mm2。A low-power digital to analog converter （DAC） was fabricated in the SMIC 0. 18 μm, 1.8 V CMOS process, and the DAC was applied in the Gaussian frequency-shift keying （GFSK） open- loop modulator system. In order to achieve a GFSK programmable modulation factor and effectively reduce the chip area and the power dissipation of the digital to analog conversion circuit, the low 7 bits of the DAC were designed to realize high speed data conversion through an R-2R ladder structure of binary weighted resistor network. At the same time, high 3 bits were designed for the programmable function of the DAC output amplitude voltage. The function was completed by adjusting the bias voltage of the R-2R ladder circuit through a logic decoding circuit. Through these methods, the GFSK modulation factor was programmable controlled. Measurement results show that the DAC effectively complete the data conversion function with 1.8 V supply voltage and 16 MHz data conversion frequency. The current consumption of DAC is 0. 55 mA, and the chip area of DAC is less than 0.02 mm2.

关 键 词：高斯频移键控(GFSK) 数模转换器(DAC) 低功耗 数模转换器 R-2R梯形 网络 锁相环(PLL) 

分 类 号：TN47[电子电信—微电子学与固体电子学]