Parameterized Integrated Power and Performance （PIPP） Model for Ultra High-Performance of TOPS level DSP  

作　　者：YANG Hui CHEN Shuming WU Tiebin 

机构地区：[1]School of Computer Science, National University of Defense Technology, Changsha 410073, China

出　　处：《Chinese Journal of Electronics》2013年第4期707-711,共5页电子学报（英文版）

基　　金：This work is supported by the National Natural Science Foundation of China （No.61070036, No.61133007）.

摘　　要：Amdahl＇s law is a simple and fundamen- tal tool for understanding the evolution of performance as a function of parallelism. Following a recent trend on timing and power analysis of general purpose many-core chip using this law, we develop a novel PIPP analytical model for evaluating the performance and power of hier- archical on-chip large-scale parallel architectures with the core number, super-node size, processing element number, and function unit number taken into consideration. We thereby investigate the influence of workload characteris- tics （Thread-level parallel TLP, Instruction-level parallel ILP and Data-level parallel DLP） on resource allocation with the restriction of performance and power. The re- sults provide some feasible options to design TOPS level DSP architecture as well as a theoretical basis for making the design more scalable.

关 键 词：Hierarchical architecture Data-level par-allel （DLP） Thread-level parallel （TLP） Instruction-levelparallel （ILP） Model. 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论] TU528.31[自动化与计算机技术—计算机科学与技术]