基于RapidIO的片上网络扩展接口设计与实现  

Design and Implementation of RapidIO Based Networks-on-Chip Extension Interface

作　　者：赵淳[1] 梁利平[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2013年第12期31-34,共4页Microelectronics & Computer

基　　金：中国科学院项目"百人计划"(KGCX2-YW-134)

摘　　要：片上网络被认为是一种适合未来多核处理器系统芯片的片上通信架构.随着片上计算资源数量的持续增多,片间通信逐渐成为影响片上计算和通信性能的重要因素.提出了一种基于RapidIO的高带宽、低延时片上网络扩展接口,用于满足多核系统芯片的片间通信需求.接口采用了层次化的设计方法以提高系统的应用灵活性,同时降低了硬件设计的复杂度.实验结果表明,扩展接口的硬件资源开销小,有效通信带宽达到8.92Gb/s.Networks-on-Chip （NoC） is considered to be a kind of viable on-chip communication fabrics for future Multiproeessor System-on-Chip （MPSoC）. With increasing amount of processing elements, on-chip computing and communication performance is heavily influenced by inter-chip communication. A high-bandwidth, low-latency RapidIO-based extension interface is proposed to meet inter-chip communication requirement of Not-based MPSoC. It is hierarchically designed to improve system flexibility while reducing hardware complexity. Experiment result shows that the hardware overhead of the extension interface is verv small, and thp offoetlvo h^n~t,~,;A,l. ;~ ~ agv＇!-.~.

关 键 词：RAPIDIO 片上网络 片间通信 扩展接口 

分 类 号：TN402[电子电信—微电子学与固体电子学]