IP路由器片上系统的设计与性能仿真  

Design and Simulation of IP Router System on Chip

作　　者：王亚刚[1] 

机构地区：[1]西安电子科技大学计算机学院,西安710071

出　　处：《系统仿真学报》2013年第12期2952-2960,共9页Journal of System Simulation

基　　金：国家自然科学基金项目(60976020);陕西省教育厅科研计划项目(2010JK833)

摘　　要：为了应对IP(Internet Protocol)路由器在性能、扩展性方面的挑战,提出并设计了一种基于大规模并行处理片上系统(MPPSoC,Massively Parallel Processing System on Chip)体系结构的IP路由器片上系统,该片上系统结构中使用大量的、同构的处理单元进行IP分组处理,并通过扩展性良好的SD-Torus(Semi-Diagonal Torus)片上网络(NoC,Network on Chip)进行片内互连,实现了分布式的转发和交换。重点研究了IP路由器片上系统中同构处理单元的结构、片内互连网络拓扑结构的选择、地址查找和分组交换功能在各个处理单元上的映射等关键问题。使用硬件描述语言SystemC,对该IP路由器片上系统进行了建模,并通过采用不同的IP分组流量模型,在不同的网络规模、不同负载程度下,对路由器片上系统的性能,包括系统吞吐量、平均延迟以及延迟抖动等关键性能参数进行了仿真。仿真结果表明,该结构具有良好的系统性能和扩展性。To meet the challenges of the IP （Intemet Protocol） router in its performance and scalability posed by the development of the Internet, an IP router SoC （System on Chip） architecture based on the MPPSoC （Massively Parallel Processing SoC） was proposed, in which a large number of the homogeneous processing elements were interconnected by a scalable SD-Torus （Semi-Diagonal Torus） network on chip, and a fully distributed forwarding and switching was achieved. The key techniques for the construction of the homogenous processing element, selection of the on-chip network topology and the mapping of the forwarding and switching functionality onto the network nodes were discussed in detail. SystemC, a hardware description language, was adopted to model the proposed IP router SoC architecture. Under different IP traffic pattern, network size and traffic load, the key performance parameters were obtained. Simulation results show that the proposed architecture has both high performance and scalability.

关 键 词：IP路由器 片上系统 片上网络 系统性能 扩展性 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]