HIRFL主加速器相位稳定系统的环路设计  

Design on Control Phase System of Electric Field Cavity Accelerator for HIRFL

作　　者：李强[1] 张红涛[1] 李靖[1] 许哲 王春晓[2] 石爱民[2] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]中国科学院近代物理研究所,甘肃兰州730000

出　　处：《无线电通信技术》2013年第6期78-81,共4页Radio Communications Technology

摘　　要：针对HIRFL(重离子加速器)的加速器腔体的高频电压设计了以DSP和FPGA为基础的数字相位负反馈控制稳定系统。介绍了相位稳定系统的组成、环路滤波器设计与参数计算方法等几个方面的内容,提出了零极点对消与重构的环路设计方案,本实现方案可以应用于各种Q值变化的加速器腔体的相位稳定控制与幅度稳定控制。设计出的设备在SSC腔体上进行了长期测试,表明设备具有优异的调制抑制度与长期相位稳定度。A design of negative phase feedback control system is proposed by utilizing DSP and FPGA based on electric field cavity accelerator for HIRFL. The composition,design project,design loop parameters,etc, are Introduced. A design method that eliminated cavity pole by zero is utilized. This design can be used to control the phase stabilization and amplitude stabilization of an RF electric field on cavity accelerator with a changed quality coefficients. The phase control system of SSC are tested in a long-term stability experiments,and the results show that the system has excellent phase stabilization in long term and parasitic phase modulation suppression.

关 键 词：相位稳定 幅度稳定 环路设计 长期稳定度 调制抑制度 

分 类 号：TL503.2[核科学技术—核技术及应用]