一种4位100MS/s超低功耗电流舵D/A转换器  

An Ultra-Low Power 4-Bit 100-MS/s Current Steering D/A Converter

作　　者：徐震[1] 骆丽[1] 魏琦[2] 李学清[2] 杨华中[2] 刘嘉男 

机构地区：[1]北京交通大学电子信息工程学院,北京100044 [2]清华大学电子工程系电路与系统研究所,北京100084

出　　处：《微电子学》2013年第6期747-750,755,共5页Microelectronics

基　　金：科技重大专项资助项目"新一代宽带无线移动通信网"(2010ZX03006-003);高等学校博士学科点专项科研基金资助项目(20110002110058);国家自然科学基金资助项目(NSFC60976024)

摘　　要：设计了一种应用于无线传感网系统的4位100 MS/s超低功耗电流舵D/A转换器(DAC)。为了满足系统超低功耗和高线性度的要求,在保证输出电压幅度不变的前提下,增加后级滤波器的输入阻抗来减小DAC的输出电流,使用均衡开关序列补偿电流源阵列中的梯度误差来获得高静态线性度。电路采用SMIC 0.13μm CMOS工艺实现,电源电压为2.5V/1V。实测结果显示,DAC的功耗仅为0.49mW,积分非线性(INL)和微分非线性(DNL)均小于0.02LSB。32MHz采样频率时,无杂散动态范围(SFDR)在整个奈奎斯特频带内均大于30dB;100MHz采样频率,9.9MHz/42.5MHz输出信号频率时,SFDR达到32.8dB/23.6dB,核心部分面积仅为0.2×0.23(mm2)。An ultra-low power 4-bit 100 MS/s current steering digital-to-analog converter （DAC） for wireless sensor network （WSN） system was proposed. In this circuit, output current was reduced by increasing input impedance of the following filter to achieve low power, while output voltage swings remained unchanged, and balanced switching scheme was used to compensate gradient errors in current source array for high static linearity. The circuit was fabricated in SMIC 0. 13μm 2.5 V/1 V standard CMOS process, and the circuit occupied a chip area of 0.2 mm × 0. 23 mrn. Test results showed that the DAC achieved DNI. and INL less than 0. 02 LSB with only 0.49 mW of power. The DAC achieved an SFDR better than 30 dB for signals from dc to Nyquist for a 32 MS/s sampling clock, and for sampling frequency up to 100 MS/s, it had an SFDR of 32. 8 dB and 23. 6 dB for an input signal frequency of 9. 9 MHz and 42.5 MHz, respectively.

关 键 词：数模转换器 电流舵 均衡开关序列 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN432