H.264变换和量化的优化设计与硬件实现  

Optimal Design of H.264 Transform and Quantization and Its Hardware Implementation

作　　者：王巍[1] 谢玉亭[1] 林涛[1] 徐巍[1] 王振[1] 

机构地区：[1]重庆邮电大学光电工程学院,重庆400065

出　　处：《微电子学》2013年第6期812-816,826,共6页Microelectronics

摘　　要：为了提高H.264/AVC变换和量化部分硬件实现的速度,通过分析整数离散余弦变换(DCT)和量化模块的速度优化设计,提出一种算法的并行流水线处理结构。这种结构可同时处理16个不同数据类型的像素点(亮度或色度),降低了计算复杂度,避免了解码端的失配问题。实验结果表明,优化后的算法吞吐量达到3 564Mpixel/s,PSNR只降低了约0.02dB,满足实时性的要求,获得了比以往标准更好的编码性能。In order to improve speed o{ transform and quantization hardware implementation of H. 264/AVC, a pipelined parallel processing architecture for the algorithm was proposed by analyzing the optimal design of the integer discrete cosine transformation （DCT） and quantization module. In this architecture, computational complexity was reduced and decoder mismatch was avoided by handling 16 different types of pixel data （luma or chroma） a time. Experimental results showed that the optimized structure for the algorithm achieved a throughput up to 3564 mega pixels per second with PSNR dropped by about 0. 02 dB, which met requirements of the algorithm for real-time operation, and a better coding performance, compared to previous standards.

关 键 词：H 264 AVC 实时性 整数离散余弦变换 量化 并行流水线 

分 类 号：TN919.81[电子电信—通信与信息系统]