微控制器射频抗扰性与受测引脚位置的关系  

Dependence of RF Immunity of Microcontroller on Location of Pin-Under-Test

作　　者：王自鑫[1] 江丽[1] 粟涛[1] 

机构地区：[1]中山大学物理科学与工程技术学院,广州510275

出　　处：《微电子学》2013年第6期871-875,880,共6页Microelectronics

摘　　要：研究了复杂集成电路电磁抗扰性与受测引脚位置的关系。通过建模分析发现,注入受测引脚的电磁杂波通过封装耦合到敏感的时钟模块,导致时钟模块失效,在抗扰性曲线上形成相关结构。因耦合与受测引脚的位置有关,所以受测引脚位置会影响到抗扰性。对样品微控制器的抗扰性进行测量,验证了上述受测引脚位置对集成电路抗扰性的影响。研究表明,即使是同类受测引脚,其位置的改变可以明显影响到抗扰性测试结果。Dependence of electromagnetic immunity of complicated integrated circmts on locanon oi pm-unucs test was studied. Analysis based on simulation showed that the electromagnetic disturbance injected on the pin under-test might reach the sensitive clock module through package coupling, which would induce failure of the clock function. Change in the pin location would shift package coupling, and influence required disturbance power for clock failure, thereby altering the tested immunity at certain disturbance frequencies, lmmunity measurements were performed on sample microcontrollers, and results supported theoretical analysis. It has been shown that, even among pins under test of the same functional type, the location of pins has an obvious effect on immunity in certain ranges near a sensitive module.

关 键 词：集成电路 微控制器 电磁抗扰性 引脚位置 

分 类 号：TN973[电子电信—信号与信息处理]