一种适用于SoC的时钟复位管理电路设计  

A Usefule Clock and Reset Management Circuit Design in SoC

作　　者：司焕丽[1] 胡杨川 

机构地区：[1]保密通信重点实验室,四川成都610041

出　　处：《通信技术》2013年第12期104-106,共3页Communications Technology

摘　　要：给出了一套适用于SoC芯片的时钟和复位管理电路设计范例,详细介绍了SoC芯片中的时钟和复位管理电路的实现方案。其中时钟管理电路支持输入时钟可选、PLL动态变频、时钟门控管理和时钟状态查询功能,能够灵活的控制各模块输入时钟开启或关闭,很好的支持SoC芯片低功耗工作模式。复位管理电路支持复位输入控制功能和复位状态查询功能。复位输入控制可以选择使能或不使能复位源触发系统复位。The paper proposes a design example of clock and reset management circuit in SoC, as well as the implementation scheme of clock and reset management circuit in detail. In this scheme, the clock man- agement circuit can choose external clock or OSC as the input of PLL and config PLL to exchange output clock frequency dynamically. The clock-gating function and clock status query function is provided. So the clock management circuit can flexibly power off clocks in SoC and SoC would come into low power mode. The reset management circuit provides reset control and reset status query function, and the circuit can control which input reset would be enabled or non-enabled.

关 键 词：SOC 时钟管理 复位管理 

分 类 号：TN492[电子电信—微电子学与固体电子学]