基于40 nm CMOS工艺可快速锁定的宽带锁相环电路设计  

Design of a Fast-Lock Phase-Locked Loop with Wide Band Width Based on 40 nm CMOS

作　　者：谭茗[1,2] 唐立军[1] 黄水龙[2] 谢海情[1] 

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410004 [2]中国科学院微电子研究所射频集成电路研究室,北京100029

出　　处：《微电子学与计算机》2014年第1期156-159,共4页Microelectronics & Computer

基　　金：03国家重大专项(2012ZX03001018-004);湖南省科技计划项目(2011GK3116)

摘　　要：通过改进鉴频鉴相器（PFD）的电路结构，增加一个控制模块自适应调整电荷泵的充放电电流大小，设计了一种可快速锁定的宽频带电荷泵锁相环电路．当鉴频鉴相器输出的相位误差值大于控制模块中的延迟时间r时，打开控制开关增加电荷泵的电流，从而增加环路带宽，减少环路滤波器的电阻值，实现快速锁定，环路稳定性不变．当环路接近锁定时，调整带宽到预设的优化值，保证了系统性能的最优化．基于SMIC40nmCMOS工艺，完成电路设计与仿真．结果表明：在电源电压为2．5V时，该锁相环可实现输出频率范围为698～960MHz，17002200MHz，2300-2700MHz，覆盖GSM，TD-SCDMA，wCDMA，TDLTE四个通讯标准的工作频段，锁定时间小于12μs.Through improving the phase frequency discriminator circuit structure, and adding a control module to control charge pump current, a charge pump phase-locked loop circuit which has the characteristics of fas〉lock and wide band has been designed. When the phase error value of the phase frequency discriminator is greater than the delay time r of the control module, the control switch is opened to increase the charge pump current, the loop bandwidth is increased, at the same time the resistance of the loop filter is reduced, realized fast lock, loop stability do not change. When the loop is close to lock, the bandwidth is adjusted to the presupposed optimization value to get a system of optimal characteristics. Based on SMIC 40 nm CMOS process, a phase-locked loop is designed, contain circuit and layout design. The results of simulation show： The output frequency covered GSM, TD-SCDMA, WCDMA, TD-LTE four communication standards working frequency band, in other words, the output frequency ranges for 698~960 MHz, 1 700~2 200 MHz, 2 30042 700 MHz with a setting time of less than 12us at a 2.5 V supply.

关 键 词：锁相环 快速锁定 宽频带 CMOS 

分 类 号：TN911.8[电子电信—通信与信息系统]