多功能数字钟电路的制作  

Design of Multi-function Digital Clock Circuit

作　　者：黄姗姗[1] 李骏[1] 

机构地区：[1]南京理工大学电光学院,江苏南京210094

出　　处：《电子质量》2013年第12期37-40,共4页Electronics Quality

摘　　要：该文是基于FPGA,采用VerilogHDL通过自下而上的设计方法完成的。根据功能将设计分为六大模块:仿电台报时、定时闹钟、时钟、日期、世界时间、显示模块,世界时间是格林威治时间,最终在Quartus II的开发环境下完成,并且使用FPGA的芯片EP2C8Q208C8完成验证。结果表明,该设计切实可行,外围电路简单,模块功能强大,满足人们的需求,在FPGA的数字时钟设计方面具有很大的参考价值。This article is based on the FPGA,which through a bottom-up and using Verilog HDL to fin-ished.According to the function which are divided into six modules：Imitation radio timekeeping,timing alarm clock,clock,date,world time,display module,the world time is Greenwich Mean Time.Final under the Quartus II development environment to compliled and simulated,and used of FPGA chip EP2C8Q 208C8 to complete verification.The results shows that the design practical and simple hardware circuit and the design is powerful,so that meet people＇s needs.The digital clock in the FPGA design has great reference value.

关 键 词：现场可编程逻辑器件 VERILOGHDL 多功能数字时钟 QUARTUSII 

分 类 号：TN79[电子电信—电路与系统]