面向磁记录信道的原模图LDPC码译码器的FPGA设计  

Protograph-based LDPC decoder applied to magnetic recording channel

作　　者：周健[1] 吕毅博[2] 洪少华[2] 王琳[2] 

机构地区：[1]重庆邮电大学重庆市移动通信重点实验室,重庆400065 [2]厦门大学信息科学与技术学院,福建361005

出　　处：《重庆邮电大学学报（自然科学版）》2013年第6期788-794,共7页Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)

基　　金：国家自然科学基金(61271241)~~

摘　　要：针对传统原模图低密度奇偶校验(low density parity check,LDPC)码在译码硬件实现中,由于采用随机扩展方式,导致数据拥塞和布线困难,继而产生译码延时和资源消耗的提高及吞吐量的下降问题,通过2步准循环扩展得到了适于硬件实现的码字结构,设计了一种面向磁记录信道的原模图LDPC码译码器。该译码器信息更新采用基于TDMP(turbo decoding message passing)分层译码的归一化Min-Sum算法使得译码器具有部分并行架构;同时为了降低译码时间及功耗,给出一种低资源消耗的提前终止迭代策略。硬件实现结果表明,该译码器的译码性能十分接近相应的浮点算法,在低资源消耗的前提下,工作频率可达183.9 MHz,吞吐量为63.3 Mbit/s,并可同时适用于多种原模图LDPC码。Using random expansion algorithm, the hardware implementation of conventional protograph-based LDPC （low density parity check） decoders has difficulty with wiring and data transmission, which results in the improvement of re- source consumption and decrease in throughput. In this paper, an easy-hardware-implementation quasi cyclic protograph- based LDPC code is obtained by the use of a two-step lifting procedure, and we also propose a protograph-based LDPC de- coder for magnetic recording channels. Utilizing the normalized Min-Sum algorithm based on the TDMP （Turbo decoding message passing） layered decoding scheme, the proposed decoder has a partially parallel architecture. Moreover, an early termination strategy is also proposed to reduce the latency and power consumption of the decoder. The proposed LDPC de- coder is evaluated on a Xilinx Spartan 6 FPGA （ field programmable gate array） platform and the results indicate that the proposed decoder requires low resource and can be utilized for multiple protograph-based LDPC codes.

关 键 词：磁记录信道 原模图LDPC码 准循环扩展 提前终止迭代策略 低资源消耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]