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机构地区:[1]北京工业大学电子信息与控制工程学院,北京100124 [2]中兴通信股份有限公司,北京100191
出 处:《高技术通讯》2013年第12期1299-1307,共9页Chinese High Technology Letters
基 金:国家自然科学基金(61001049);北京市自然科学基金(4112012);北京市教委科技成果转化(61001049)资助项目
摘 要:针对一般多元LDPC译码器时延大、吞吐量低的局限,设计了一种基于EMS算法的新型多元LDPC译码器。它根据前向后向算法规则,以3路单步运算单元完成校验节点更新,使得所需时钟周期约降为一般结构的1/3;采用低复杂度全并行运算的变量节点信息更新单元,无需利用前向后向算法将更新过程分解为多个单步运算,消除了变量节点更新的递归计算;采用新的双进双出信息调度算法,进一步降低了变量节点更新复杂度且提高了译码器吞吐量。通过Xilinx Virtex-4平台对一个GF(16)域上(480,360)的准循环多元LDPC码进行了综合仿真,结果表明,它以较小的逻辑资源消耗为代价提高了近3倍的吞吐量。For the conventional extended rain-sum (EMS) decoding algorithm for nonbinary quasicyclic LDPC ( QC-LD- PC) coder,it is necessary to perform quantities of recursive computation among the message vector, and only one single step operations is utilized to complete the check node update, which leads to larger decoder latency. In this paper, a novel non-binary LDPC decoder architecture is proposed to overcome this problem. Based on the rules of forward-backward algorithm ,we utilize three single step operations to complete the check node update and optimize the check node update step operation. The hardware resource consumption for check node update increases, but the cycle required is reduced to 1/3 of the common decoder structure' s. The variable node update unit with fully parallel computation is presented without forward-backward, which removes recnrsive computation among the message vector. Furthermore, double-input and double-output information scheduling algorithm is used to improve the throughput of the decoder and reduce the complexity of computation on variable node update further. Moreover, an FPGA implementation of a (480,360) nonbinary QC-LDPC decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques. Simulation results show that the proposed scheme can triple throughput of the decoder at the cost of less hardware resource consumption.
分 类 号:TN911.22[电子电信—通信与信息系统]
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