AVS环路滤波器的FPGA优化及实现  

Optimization and Implementation of AVS Loop Filter on FPGA

作　　者：刘博[1] 王永霞[1] 张刚[1] 

机构地区：[1]太原理工大学通信与嵌入式系统实验室,山西太原030024

出　　处：《电视技术》2014年第1期55-57,81,共4页Video Engineering

基　　金：国家自然科学基金项目(60772101)

摘　　要：针对AVS环路滤波的算法原理,用VHDL语言完成了在FPGA硬件平台上的设计和仿真实现。环路滤波器对滤波数据的存储结构进行了合理的安排,用连续地址和跳变地址相结合的方式读取数据,并实现了读取数据的同时并行进行计算操作,减少了环路滤波所占用的时钟周期,提高了计算效率。该设计基于Xilinx公司的Virtex-4平台实现,最高时钟频率可达到140 MHz,满足AVS实时编码要求。In this paper, design and simulation implementation of AVS loop filter are accomplished on FPGA hardware platform with VHDL language corresponding to relevant algorithm principles. For the loop filter designed, the storage structure of filter data is arranged reasonably, the data is read by means of combining contiguous address and jumps address together and computation operation is performed in parallel while reading data, reducing the clock cycles consumed by loop filtering and improving computation efficiency. This design is executed on Xilinx Virtex-4 with the maximum frequency up to ldO MHz, which satisfies the real - time encoding demand of AVS.

关 键 词：AVS 环路滤波器 FPGA 

分 类 号：TN919.8[电子电信—通信与信息系统]