一种基于LPC2102芯片的倍频器设计方案  

Design scheme for frequency multiplier based on LPC2102 chip

作　　者：刘新红[1] 

机构地区：[1]北京信息职业技术学院,北京100015

出　　处：《数字通信》2013年第6期61-63,80,共4页Digital Communications and Networks

摘　　要：设计用LPC2102实现倍频的硬软件,并通过Proteus进行仿真验证。结果表明:通过改变倍频数能够方便地实现不同倍频数的倍频功能。将仿真结果和理论计算的倍频最大输入频率进行对比。使用定时器T0的捕获功能实现对输入信号周期的测量,使用定时器T1的匹配功能产生倍频后的输出信号。通过将输入信号每2个上升沿为一组进行分组,测定输入信号周期只需1个周期。每组中在第二个上升沿中断中复位匹配定时器来消除误差累积,实现输入、输出信号同步。In this article, both hardware and software are designed to realize frequency muhiplicalion using LPC2102. The design is simulated and verified by Proteus. The results show that the frequency multiplier function can be conveniently re- alized by changing multiplier factors. Maximum input frequency is compared between simulation and theofitical calculation. The period of input signal is measured using capture function of timer TO. Output signal is generated using match function of timer T1. Every two rising edges are divided into one group. So measuring input signal period can be finished in one pe- riod and can better trace change of the input signal. In the interruption caused by the second rising edge, timer T1 is reset to avoid error accumulation so that input signal and output signal synchronization can be achieved.

关 键 词：倍频器 LPC2102 最大输入频率 输入输出同步 

分 类 号：TN771[电子电信—电路与系统]