基于时钟信号的异步时序逻辑电路设计  

Design of Asynchronous Sequential Logic Circuit Based on the Clock Signal

作　　者：陈华[1] 周家萍[1] 

机构地区：[1]兴义民族师范学院,贵州兴义562400

出　　处：《兴义民族师范学院学报》2013年第4期120-121,共2页Journal of Minzu Normal University of Xingyi

摘　　要：与其他异步时序逻辑电路设计方法相比,基于时钟信号的设计法更简便、快捷。使用该方法时,不用画出时序图,直接从次态卡诺图中选定正确的时钟信号,再快速求出触发器状态方程。Compared with other asynchronous sequential logic circuit design method, design method based on the clock signal is more convenient, shortcut. The method is used, do not draw the timing diagram, select the correct clock signal directly from the states of Kano, and then to obtain rapidly trigger state equation.

关 键 词：异步时序逻辑电路 时钟信号 次态卡诺图 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]