双基地雷达目标速度计算的FPGA实现  

Computing the target velocity of the bistatic radar based on FPGA

作　　者：宋万均 张安堂[1] 

机构地区：[1]空军工程大学防空反导学院,陕西西安710051

出　　处：《电子技术应用》2014年第1期47-49,52,共4页Application of Electronic Technique

摘　　要：为了解决双基地雷达目标速度计算复杂的问题,基于CORDIC算法并利用FPGA设计了双基地雷达目标速度计算模块。仿真结果表明,所设计的双基地雷达目标速度计算模块计算精度高,工作速度快,资源消耗少,能很好地应用于双基地雷达中。In order to solving the complexity of computing the velocity of the bistatic radar＇s target, this paper designs a mod- ule that computes the velocity of the bistatic radar＇s target based on the CORDIC arithmetic and FPGA chip. The simulation results indicate that the module designed in this paper has high computing precision and fast working speed, and the module uses few chip resource. So it can be applied into bistatic radar very well.

关 键 词：双基地雷达 CORDIC算法 FPGA 

分 类 号：TN713[电子电信—电路与系统]