锁相环电源噪声激起的抖动灵敏度研究  

Power-supply Noise Induced Jitter Sensitivity in PLL

作　　者：常博皓 林永嘉[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子科技》2014年第2期62-65,共4页Electronic Science and Technology

摘　　要：锁相环作为噪声敏感器件,最大干扰源来自电源噪声。为实现系统的高性能,盲目降噪是很多工程师唯一手段。文中指出,不同频点电源噪声对PLL造成的抖动不同,而单纯降噪可能导致过度设计且不能达到目的。文中通过搭建锁相环Spice模型,开发的一款软件作为论证工具来阐述抖动灵敏度概念。PLL is noise-sensitive devices and power-supply noise is the largest source of interference. For a high system performance, reducing power-supply noise is the only choice for most engineers. The concept is presen- ted in the paper that power-supply noise induced jitter in different frequencies is different and that reducing noise a- lone may lead to over-design or failure. A SPICE model of PLL is built and self-developed software is used to illus- trate the concept of jitter sensitivity.

关 键 词：锁相环 电源噪声 SPICE 抖动灵敏度 

分 类 号：TN911.6[电子电信—通信与信息系统]