基于DDS和PLL技术实现的L波段高码速率(16Mb/s)最小频移键控调制源  

L-bandHigh Code Rate(16Mb/s)MSK Modulation Source Based on DDS and PLL Technology

作　　者：杨杰[1] 杨光[1] 孙敏[1] 宋烨曦[1] 

机构地区：[1]四川九洲电器集团有限责任公司,绵阳621000

出　　处：《科学技术与工程》2014年第1期209-213,共5页Science Technology and Engineering

摘　　要：介绍了一种实现MSK调制信号的方法。该方法结合了DDS和PLL技术的特点,采用二次混频方案,实现了码速率达16Mb/s的L波段(1 030MHz和1 090MHz)MSK调制信号源。对调制后的信号质量进行了测试,并通过测试结果对DDS系统时钟与FPGA系统时钟同步的重要性进行了说明。测试结果表明该信号源的EVM RMS值最大为6.7%(在1 030MHz时测得),最小仅为2.3%(在1 090MHz时测得),并且当DDS系统时钟与FPGA系统时钟同步时,其调制信号的信号质量要大大优于两者不同步时的信号质量。A method has been introduced to realize MSK modulation signals. This method combines the characteristics of DDS and PLL technology, using twice-mixing solutions to achieve a L-band （1 030 MHz and 1 090 MHz） MSK modulation signal source, of which code rate is up to 16 Mb/s. Modulated signal quality has been tested and the importance of the synchronization of DDS system clock and FPGA system clock is also described. Test results show that the maximum value of EVM RMS of this signal source is 6.7%（when measured at 1 030 MHz）, and the minimum value is only 2.3% （when measured at 1 090 MHz）, and when DDS system clock and FPGA system clock is synchronous, the modulated signal quality is much better than that which is tested when DDS system clock and FPGA system clock is asynchronous.

关 键 词：最小频移键控(MSK) 误差向量幅度(EVM) 锁相环(PLL) 直接数字频率合成(DDS) 

分 类 号：TN761.93[电子电信—电路与系统]