用于验证工艺开发包的测试芯片自动生成流程  

Test Chip Automatic Generation Flow for Process Development Verification

作　　者：刘得金[1] 史峥[1] 胡龙跃[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,杭州310027

出　　处：《计算机工程》2014年第2期314-316,共3页Computer Engineering

基　　金：国家自然科学基金资助项目"面向28-14nm的高空间分辨率工艺偏差在线检测关键技术研究"(61204111)

摘　　要：在工艺开发包的验证过程中,需要手动地在版图编辑器中对参数化单元进行实例化和摆放绕线,由此产生大量测试芯片。为此,提出一种用于验证工艺开发包的测试芯片自动生成流程,采用软件接口产生Skill脚本和工艺开发包交互,以获取工艺开发包的信息、发送命令对工艺开发包进行操作的方法,能自动地对参数化单元予以实例化,自动地摆放绕线,并实现测试芯片版图的布局规划。用该软件接口针对某代工厂的40 nm半导体工艺开发包开发一套测试芯片,产生一条测试芯片的平均时间为5.2 s左右,结果证明该方法是有效的,能缩短工艺开发包的验证时间。For the problem that there are lots of works to do including instantiating and placing and routing parameterized cells to generate huge amount of test chips in the layout editor manually in the process development verification flow, an automatic flow of test chip generation for process development verification is raised. A software interface that generates skill script is used to get information about process development and communicate with and send command to them. The method can help instantiate and place and route parameterized cells as well as floor planning automatically. The software interface is used to develop test chips for a 40 nm semiconductor technology process design kits. The average time to generate a test chip by this software interface is 5.2 s. The result approves that the method is efficient and can decrease the time to verify process design kits.

关 键 词：工艺开发包 测试芯片 参数化单元 实验数据设计 可制造性设计 电子设计自动化 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]