A 4 GHz CMOS multiplier for sigma–delta modulated signals  

作　　者：郭晓丹 孟桥 梁勇 

机构地区：[1]Institute of RF- & OE-ICs, Southeast University [2]Engineering Research Center of RF-ICs & RF-Systems, Ministry of Education

出　　处：《Journal of Semiconductors》2014年第1期91-95,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.60576028)

摘　　要：An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.

关 键 词：CMOS sigma-delta modulation MULTIPLIER bit-stream 

分 类 号：TN911.3[电子电信—通信与信息系统]