用遗传算法实现CMOS时序电路最大功耗估计  

Maximum Power Estimation for CMOS Sequential Circuits by Genetic Algorithm

作　　者：卢君明[1] 林争辉[1] 

机构地区：[1]上海交通大学大规模集成电路研究所,上海200030

出　　处：《微电子学》2001年第1期6-9,19,共5页Microelectronics

基　　金：美国国家科学基金! (NSF;U .S.A);国际合作项目! (5 978East Asia and Pacific Program - 96 0 2 485 )

摘　　要：最大功耗分析对于设计高可靠性的 VLSI芯片是非常重要的。实际中 ,总是在有限的计算时间内获取一个近似最大功耗。文中用遗传算法来选择具有高功耗的输入及内部状态模型 ,对电路进行仿真 ,实现时序电路的最大功耗估算 ;同时 ,实现了基于统计的逻辑模拟最大功耗估计方法。基于 ISCAS89基准时序电路的仿真表明 ,新方法在大规模门数时具有明显的优势 ,估算精度较高。Estimation of maximum power dissipation is important in designing highly reliable VLSI systems However, maximum power estimation for CMOS circuits is essentially a combination optimization problem, which has exponential complexity in the worst case For large-scaled sequential circuits, due to the fact that the sequential relationship between the Primary Inputs and States must be considered, it is more CPU time intensive to exhaustively search for the optimal input patterns to induce maximum power In this paper, a novel approach is proposed to obtain a lower bound of the maximum power consumption using Genetic Algorithm (GA) Experiments with ISCAS-89 benchmark circuits show that our approach generates the lower bound with the quality that cannot be achieved using simulation-based techniques In addition, a Monte Carlo based technique to estimate maximum power dissipation is realized

关 键 词：CMOS 时序电路 功耗估计 遗传算法 

分 类 号：TN432.02[电子电信—微电子学与固体电子学]