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作 者:廖银[1] 姜海涛[1] 孙广中[1] 靳国杰[2] 陈国良[1]
机构地区:[1]中国科学技术大学计算机科学与技术学院,合肥230027 [2]中国科学院计算技术研究所,北京100190
出 处:《小型微型计算机系统》2014年第3期520-525,共6页Journal of Chinese Computer Systems
基 金:国家自然科学基金重点项目(61033009)资助;工信部科技重大专项(2009ZX01028-002-003)资助
摘 要:如何提高性能是动态二进制翻译中的核心研究问题.动态二进制翻译技术以分支指令结尾的基本块是翻译和执行的基本单元,基本块之间的跳转关系由分支指令确定.间接分支的目标地址在运行时才能确定,优化比较困难.已有工作表明间接分支目标地址的处理是影响动态二进制翻译系统性能的重要因素.经过我们的实验分析表明间接分支的目标地址分布具有较好的局部性,在此基础上提出一个带私有缓存的间接分支目标的查找算法,利用私有缓存对间接分支的目标地址进行预测,分支目标良好的局部性带来了高的预测成功率,从而减少了上下文切换的次数,并且使得X86体系结构下SPEC CPU2000 INT测试集程序在龙芯平台上翻译执行时间平均减少了10%-20%.How to improve performance is a core research issues in dynamic binary translation ( DBT ). The basic block that ends with branch instruction is basic unit of the translation and execution in DBT technology. Jump relationship between the basic block is deter- mined by the branch instruction. The target address of indirect branch~ IB ) is determined at run time and varies greatly. Many resear- ches have shown that how to handle the indirect branch is a key impact on the performance of DBT. Our experiment indicates that dis- tribution of IB' s target address has a good locality. In order to make use of the locality, this paper proposes a novel algorithm the u- sing a private cache to cache target address for prediction. For the good locality, the private cache has a very high hit rate. This algo- rithm reduce the number of context switching for indirect branch processing. It also reduces by 10% -20% of the running time of the SPEC CPU2000 INT x86 program translated on the Loongson CPU platform.
分 类 号:TP391[自动化与计算机技术—计算机应用技术]
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