低功耗高集成度CMOS神经信号放大器  

A low-power area-efficient CMOS amplifier for neural recording applications

作　　者：杜智超[1] 张旭[1] 刘鸣[1] 陈弘达[1] 

机构地区：[1]中国科学院半导体研究所集成光电子学国家重点联合实验室,北京100083

出　　处：《高技术通讯》2014年第1期104-110,共7页Chinese High Technology Letters

基　　金：973计划(2011CB933203);863计划(2012AA030308);国家自然科学基金(61076023;61178051)资助项目

摘　　要：针对传统电容耦合-电容反馈型神经信号放大电路芯片面积过大、输入电阻低的缺陷,设计并实现了一款16通道带通胞外神经信号放大器。它通过采用新型的交流耦合T型电容网络反馈式拓扑结构,在保证低噪声和高输入阻抗的前提下减少了芯片的面积。芯片每个通道的中频增益为40.6dB,直流增益为0 dB。其-3dB高频截止频率为5kHz,而其低频截止频率可以通过调节晶体管的栅电压而进行优化。在供电电压为±1.65V的情况下,芯片在记录多通道局部场电位(LFPs)时,从1Hz到10kHz频率积分得到的输入参考噪声为4.99μVrms,其每通道功耗为19.8μW。芯片总面积为2062.5μm×525.7μm,平均每通道0.02 mm^2,由0.35-μm CMOS N-well 2P4M工艺实现。相比于传统结构的CMOS神经信号放大器,该设计在集成度及功耗上占优势。Aiming at traditional integrated neur-signal amplifiers with capacitive-couple and capacitive-feedback topology may result in overlarge chip area and relative low input impedance,a bandpass 16-channel CMOS amplifier for ex- tracellular neural recording was designed and implemented. The amplifier adopts a novel AC-coupled and T-type ca- pacitive-feedback network topology to reduce its chip area while guaranteeing its low noise and high input imped- ance. Each channel of the amplifier has a mid-band gain of 40.6 dB and a DC gain of 0dB. The-3 dB upper cut-off frequency of the amplifier is 5 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action po- tentials located in different bands. Under the supply of ± 1.65V ,it has an input-referred noise of 4.99 μVrms inte- grated from 1 Hz to 10 kHz for recording the local field potentials（LFPs） and the mixed neural spikes with a power dissipation of 19.8 μW per channel. The 2062.5μm × 525.7 μm prototype chip （ about 0.02 mm2 per channel） was designed and fabricated in the 0.35-μm N-well CMOS 2P4M process, which increases the area-efficient and decrea- ses the power.

关 键 词：神经信号放大器 T型电容反馈网络 高集成度 输入阻抗 低功耗 

分 类 号：TN722[电子电信—电路与系统]