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作 者:Chenyang Ge Zuoxun Hou Huimin Yao Nanning Zheng Wenzhe Zhao
机构地区:[1]Institute of Artificial Intelligence and Robotics, Xi’an Jiaotong University
出 处:《Chinese Science Bulletin》2014年第5期459-467,共9页
基 金:supported by the Important Specific Projects of National Science and Technology of China(2009ZX01033-001-010)
摘 要:This paper presents a new implementation of a high-definition image-processing engine,which mainly targets the 3-dimensional(3D)visualization and stereo video stream display of binocular display equipment.The engine is compatible with the mainstream analog and digital stereo videos in component format and is able to receive stereo composite video broadcast signals using an integrated analog stereo video decoder.The four modules include a spatiotemporal scaling transform engine,a 2D–3D converter,an image animating engine,and a 2D scalar operating in pipeline architecture to implement the video format conversion and the stereo effect enhancement.Furthermore,the data access,hardware structure,and system-level configurations are optimized.Finally,the proposed architecture is realized by 0.18 lm CMOS technology.The application-specific integrated circuit verification results show that the engine can generate a strong feeling of 3D immersion and highdefinition image quality with minimal flicker.The chip has wide compatibility and an uppermost 1080P-processing capacity,which has approximately 3.5 million gates with about 43 mm2 die size.This paper presents a new implementation of a high-definition image-processing engine, which mainly tar- gets the 3-dimensional (3D) visualization and stereo video stream display of binocular display equipment. The engine is compatible with the mainstream analog and digital stereo videos in component format and is able to receive stereo composite video broadcast signals using an integrated analog stereo video decoder. The four modules include a spatio- temporal scaling transform engine, a 2D-3D converter, an image animating engine, and a 2D scalar operating in pipe- line architecture to implement the video format conversion and the stereo effect enhancement. Furthermore, the data access, hardware structure, and system-level configurations are optimized. Finally, the proposed architecture is realized by 0.18 pm CMOS technology. The application-specific integrated circuit verification results show that the engine can generate a strong feeling of 3D immersion and high- definition image quality with minimal flicker. The chip has wide compatibility and an uppermost 1080P-processing capacity, which has approximately 3.5 million gates with about 43 mm2 die size.
关 键 词:图像处理引擎 数字立体声 三维可视化 显示设备 视频流 模拟立体声 视频格式转换 CMOS技术
分 类 号:TP391.41[自动化与计算机技术—计算机应用技术]
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