基于总线访问的片上调试方法研究  

Researching of On- chip Debug Based on Bus Access

作　　者：张鹏[1] 樊晓桠[1] 黄小平[1] 

机构地区：[1]西北工业大学计算机学院,西安710129

出　　处：《计算机测量与控制》2014年第2期510-512,518,共4页Computer Measurement &Control

基　　金：国家自然基金(60773223;61003037;60736012);西北工业大学基础研究基金项目(JC20110224)

摘　　要：支持片上在线调试是嵌入式SoC设计目标之一;现有的片上调试系统多基于扫描链技术,SoC系统的功能设计和调试设计必须同步,这种紧耦合的设计方法移植性差、通用性弱,与SoC系统IP复用的理念不符;基于此,提出了一种基于片上标准总线的SoC在线调试方法,该方法引入调试主设备的概念,复用片上总线传输实时调试数据,实现了对SOC外围IP的在线调试,同时通过引入调试支持单元和调试处理模块实现了对处理器主设备的总线访问调试;该方法适用于以标准总线结构互联的SOC系统,具有适用性广、调试功能丰富、调试接口多样、调试效率高等优点;该方法在以SPARC处理器为处理核心、AMBA总线为互联的SoC系统中进行了实现和在线调试验证,实验表明满足SoC的调试需求。Supporting the on--chip debugging is one of the design goals of SoC. Most of the existing on--chip debug designs are based on the technology of scan chain. The design of functional structure and debug structure are tightly coupled, it is hard to reuse the debug struc- ture. To solve the problem, the paper presents an on--chip debug method for SoC of bus architecture. The system reuses On Chip Bus as the transmission path for debug data, debug of slave IP is easily implemented through debug master. Debug Support Unit and Debug Handle U- nit in system make debug of processor a form of bus access as well. The method can be widely used. It is rich in debug function and has few limitation of debug interface and it＇ s very efficient. The method has been implemented and verified in a SoC of AMBA architecture which has a processor of SPARC architecture. The experiment indicates that the design meet the demand of SoC debug.

关 键 词：片上调试 SOC 片上总线 

分 类 号：TP306[自动化与计算机技术—计算机系统结构]