A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory  

作　　者：谯凤英 潘立阳 伍冬 刘利芳 许军 

机构地区：[1]Institute of Microelectronics,Tsinghua University [2]Tsinghua National Laboratory for Information Science and Technology

出　　处：《Journal of Semiconductors》2014年第2期36-41,共6页半导体学报（英文版）

基　　金：Project supported by the National Key Basic Research Program(No.2011CBA00602);the National Natural Science Foundation of China(Nos.61106102,61176033)

摘　　要：In order to minimize leakage current increase under total ionizing dose （TID） radiation in high density memory circuits, a new isolation technique, combining deep trench isolation （DTI） between the wells, local oxi- dation of silicon （LOCOS） isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator （PD-SOI） technology. This ra- diation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single tran- sistors under 1 Mrad（Si） radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad（Si）, with only 50% increase of the active power consumption in read mode.In order to minimize leakage current increase under total ionizing dose （TID） radiation in high density memory circuits, a new isolation technique, combining deep trench isolation （DTI） between the wells, local oxi- dation of silicon （LOCOS） isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator （PD-SOI） technology. This ra- diation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single tran- sistors under 1 Mrad（Si） radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad（Si）, with only 50% increase of the active power consumption in read mode.

关 键 词：total ionizing dose isolation leakage flash memory silicon on insulator 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]