基于wb_conmax的Wishbone二级总线设计与应用  

Design and application of two level Wishbone bus based on wb_conmax

作　　者：朱秀斌[1] 

机构地区：[1]淄博职业学院电子电气工程系,山东淄博255314

出　　处：《电子技术应用》2014年第3期22-24,28,共4页Application of Electronic Technique

摘　　要：SoC技术是嵌入式系统设计中重要的设计方法,而在SoC系统中如何将各种IP核互联在一起对嵌入式设计效率影响极大。对常见的片上总线进行比较后,选用OpenCores组织的Wishbone总线进行设计。提出了基于OpenCores组织发布维护的wb_conmax的Wishbone二级总线设计。通过对Wishbone总线的二级扩展,使得SoC系统能够更方便地集成多个IP,同时为低功耗要求的设计提出了功耗优化的策略。通过对基于AEMB的最小SoC系统在两种系统结构下的应用分析,验证了二级总线结构对于低功耗设计的可行性。SoC is an important method in embedded system.It is critical to interconnect a variety of IP core.The paper compares the four kinds common on-chip bus and decides to use Wishbone bus from OpenCores organization to design the SoC system.This paper puts forward two level bus based on wb_conmax that was released and maintended by OpenCores organization.Through the expansion of the secondary Wishbone bus,the design allowes the SoC system to integrate multiple IP more easily,while low-power requirements of the design can be obtained by the power optimization strategy.Finally,we compare the two different smallest SoC system based on AEMB system structure that adapts the single bus and two level bus structure respectively.The Results verify that the two level bus is feasible in low-power design of SoC.

关 键 词：wb_conmax 二级总线 片上系统 

分 类 号：TB51[理学—物理]