基于FPGA的高清AVS熵编码硬件设计  

FPGA-based hardware design of HD entropy coding in AVS

作　　者：张贞雷[1] 王祖强[1] 蒋霞[1] 李文军[1] 

机构地区：[1]山东大学信息科学与工程学院,山东济南250100

出　　处：《电子技术应用》2014年第2期42-45,48,共5页Application of Electronic Technique

摘　　要：为实现高清AVS熵编码硬件设计,通过对算法模块进行分析,将码表切换、码字计算和指数哥伦布编码设计成流水线并行处理单元。利用并行zig-zag扫描,加快了处理速度。同时采用组合逻辑实现码表查找,设计码长确定器,节省了硬件资源。To implement hardware design of HD AVS entropy coding, through analysis of the algorithm module, code table switching, computing of codeword and exponential-Golomb encoding are designed to pipeline processing unit. Parallel zig-zag scan is taken to accelerate the speed of processing. At the same time, combinational logic which implements code table switching and code length determiner is taken to save the hareware resources.

关 键 词：AVS 熵编码 高清 流水线 码长确定器 

分 类 号：TN919.8[电子电信—通信与信息系统]