并行可配置的HEVC熵编码的VLSI结构  

Configurable and parallel of VLSI hardware structure for entropy encoding of HEVC

作　　者：路伟[1] 余宁梅[1] 南江涵 王冬芳[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,西安710048

出　　处：《计算机工程与应用》2014年第3期121-124,144,共5页Computer Engineering and Applications

基　　金：陕西省自然科学基础研究计划项目(No.2011JQ8032);陕西省重点学科建设专项资金(No.107080903)

摘　　要：提出了一种并行的可配置HEVC熵编码的VLSI结构。通过对HEVC参考软件算法分析,针对HEVC中CABAC编码采用高度并行的语法元素处理方式,设计了针对CABAC中语法元素并行处理的硬件结构。同时采用可配置的PE-Array结构,在提高了吞吐率和计算效率的同时,平衡了VLSI设计中面积过大的问题。在SMIC 0.13μm工艺库下,进行了逻辑综合,系统总门数为16.2 K,片上存储为20.8 KB。在时钟频率300 MHz下,可处理3 840×2 160@30 frame/s的视频序列。VLSI architecture for parallel and configurable entropy coding of HEVC is proposed. By reference software algorithm of HEVC analysis, the CABAC encoding for HEVC syntax elements using highly parallel processing, it designs parallel processing hardware architecture for CABAC syntax elements. At the same time, the configurable PE-Array struc-ture can be used. While improving throughput and computational efficiency the problem of excessive area in VLSI design is solved. After logic synthesis using SMIC 0.13μm standard cell library, the number of gates is 16.2 K, and chip cache is 20.8 KB. This design can handle 3 840×2 160@30 frame/s under the working frequency of 300 MHz.

关 键 词：基于上下文模型的二进制算术编码 高效视频编码技术 可配置 超大规模集成电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]