6.5GHz锁相环单片集成电路设计  

Design of 6.5 GHz Phase-Locked Loop MMIC

作　　者：汤晓东[1] 孟志朋[1] 

机构地区：[1]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《半导体技术》2014年第3期174-178,192,共6页Semiconductor Technology

摘　　要：设计了一个锁相环频率合成器芯片,该芯片可用在无线接收系统的发射上变频和下变频中实现本振功能。该芯片通过外接滤波器和压控振荡器,构成完整的锁相环频率合成器。芯片的结构包括低相噪数字鉴频鉴相器、可编程参考分频器、双模预分频与A计数器和B计数器构成的N分频器、低温漂基准源、高精度电荷泵和4个24 bit的寄存器等。基于0.35μm SiGe工艺,芯片面积为1.4 mm×1.7 mm,归一化本底噪声-222 dBc/Hz,6.5 GHz时电流约为23 mA。基于芯片宽射频输入范围的特点,很多高频系统可省略倍频器,从而简化系统结构,降低成本。The design of a phase-locked loop （PLL） frequency synthesizer chip was presented. The chip can realize the function of vibration in the up-conversion and down-conversion sections of wireless receivers and transmitters. By using an external loop filter and voltage controlled oscillator （VeO） , a complete phase-locked loop can be implemented. The chip consists of a low noise digital phase frequency detector （PFD） , a programmable reference divider, an N divider implemented of the A and B counters in conjunction with the dual-modulus prescaler , a temperature-insensitive band-gap-reference bias and a high precision charge pump and 4 registers of 24 bit. Based on the O. 35 fLm SiGe process, the area of the PLL chip is 1. 4 mm× 1. 7 mm , the normalized background noise of the PLL chip is -222 dBc/Hz, and the current is 23 mA with the frequency of 6. 5 GHz. Based on the characteristics of the chip wide RF input range, the frequency doublers can be eliminated in many high frequency systems to simplify the system architecture and reduced cost. Key words： phase-locked loop （PLL）; phase frequency detector （PFD）; divider; normalized background noise; SiGe

关 键 词：锁相环(PLL) 鉴频鉴相器(PFD) 分频器 归一化本底噪声 SIGE 

分 类 号：TN43[电子电信—微电子学与固体电子学]