闪存控制器中BCH解码器的VLSI设计  

VLSI design of BCH decoder in NAND flash controller

作　　者：郑朝霞[1] 丁明鹏[1] 钟建福[1] 李继承[2] 

机构地区：[1]华中科技大学光学与电子信息学院,湖北武汉430074 [2]华中科技大学电子与信息工程系,湖北武汉430074

出　　处：《华中科技大学学报（自然科学版）》2014年第1期93-97,共5页Journal of Huazhong University of Science and Technology(Natural Science Edition)

基　　金：国家自然科学基金资助项目(61006020)

摘　　要：为满足闪存控制器中BCH解码器对速度和面积的要求,设计了一种高速小面积BCH(8528,8192,24)解码器,其关键方程电路采用简化的RiBM算法,利用二进制BCH码的特性简化关键方程电路结构和迭代轮数.使用关键方程电路的可折叠特性和逻辑资源复用,对解码器架构进行了面积优化,结果显示:与传统iBM算法相比,电路的关键路径延时减小了约50%,与RiBM算法相比,关键方程迭代轮数减少了1/2,电路资源减少了约1/3;该系统架构能够在保证吞吐率的前提下减小约70%电路面积.In order to meet the speed and area requirement of BCH （Bose-Chaudhuri-Hocquenghem） decoder in NAND Flash memory controller,a high speed small area BCH （8528,8192,24）decoder was designed.Simplified RiBM （Reformulated inversionless Berlekamp-Massey）algorithm was ap-plied to solve the key equation.The key equation circuit structure and iteration rounds were simplified by taking advantage of binary BCH code′s character.By using the foldable character of the key equa-tion circuit and logical resource multiplexing,the decoder architecture in area was optimized.The re-sult shows that the critical path delay reduces by about 50% compared with the traditional iBM （inve-rsionless Berlekamp-Massey）algorithm.The key equation circuit’s iteration rounds reduce half and resource reduces by about 1/3 compared with RiBM algorithm.The synthesizing result shows that the architecture can reduce by about 70% of the circuit area while keeping almost the same throughput.

关 键 词：BCH 码 闪存存储器 纠错码 BERLEKAMP-MASSEY算法 折叠结构 error correction codes (ECC) 

分 类 号：TN47[电子电信—微电子学与固体电子学]