Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects  

作　　者：XIE Qian LIANG RenRong WANG Jing LIU LiBin XU Jun 

机构地区：[1]Tsinghua National Laboratory for Information, Science and Technology, Institute of Microelectronics,Tsinghua University

出　　处：《Science China(Information Sciences)》2014年第4期224-230,共7页中国科学（信息科学）（英文版）

基　　金：supported in part by State Key Development Program for Basic Research of China(Grant No.2011CBA00602);National Natural Science Foundation of China(Grant Nos.60876076,60976013)

摘　　要：In this paper, a three-dimensional （3-D） analytical model for short-channel effects （SCEs） in a nanoscale triple-gate （TG） FinFET is derived based on solving a boundary value problem using the 3-D Poisson＇s equation. This model is validated using 3-D numerical simulations （TCAD Sentaurus）. Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness （D） or height （H）. On the other hand, when fixing the drive capability of turn-on current, i.e. fixing the total width of the conductive channel, and changing the ratio of D and H, there exists a case where SCEs are worst, and SCEs can be reduced by either increasing or decreasing the ratio from the worst case. This SCEs model can be used to predict the minimum channel length （Lmin） of a device when D, H, and tox are fixed, while keeping SCEs at a tolerable level. Based on the analytical model, the insights into the physics of SCEs in nanoscale TG FinFET are discussed, and design considerations are investigated.In this paper, a three-dimensional （3-D） analytical model for short-channel effects （SCEs） in a nanoscale triple-gate （TG） FinFET is derived based on solving a boundary value problem using the 3-D Poisson＇s equation. This model is validated using 3-D numerical simulations （TCAD Sentaurus）. Results show that SCEs in a TG FinFET can be controlled by reducing either the fin thickness （D） or height （H）. On the other hand, when fixing the drive capability of turn-on current, i.e. fixing the total width of the conductive channel, and changing the ratio of D and H, there exists a case where SCEs are worst, and SCEs can be reduced by either increasing or decreasing the ratio from the worst case. This SCEs model can be used to predict the minimum channel length （Lmin） of a device when D, H, and tox are fixed, while keeping SCEs at a tolerable level. Based on the analytical model, the insights into the physics of SCEs in nanoscale TG FinFET are discussed, and design considerations are investigated.

关 键 词：triple-gate FinFET short-channel effects （SCEs） scale length design considerations modeling 

分 类 号：TN386[电子电信—物理电子学] TN386.1