基于访问区域特征的高速地址翻译方法  

High speed address translation method based on the memory access region attribute

作　　者：王荣华[1] 孟建熠[1] 陈志坚[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2014年第2期348-353,共6页Journal of Zhejiang University：Engineering Science

基　　金：中央高校基本科研业务资助项目(2012QNA5004)

摘　　要：针对系统级二进制翻译器在虚拟／物理地址转换中出现的性能瓶颈问题，提出一种基于指令、数据和堆栈等访问区域特征的快速地址转换方法．该方法在翻译态时识别不同区域的内存访问指令，并根据区域特征采取不同的优化算法，对于指令区域和数据区域采用编译时地址转换算法，对于堆栈区域采用连续页面映射算法．在开源高速指令模拟器QEMU上运行嵌人式CPU测试基准程序PowerStone．结果表明，运行态地址转换过程减少了1％～65％，运行态执行周期数减少了11％～38％．To accelerate the speed of virtual/physical address translation in system-level binary translation, a high speed address translation method based on the memory access region attribute was proposed. Memory access instructions of different region was identified in the translation state and corresponding optimization algorithm for different memory region was implemented. Compiling based translation algorithm was adopted for instruction and data region. Consistency page translation algorithm was adopted for stack region. The results of running powerstone on the QEMU emulator shows that the address translation process in execute state decreases by 1%-65% and the total executed cycle decreases by 11% to 38 %.

关 键 词：内存访问区域属性 系统级二进制翻译器 快速地址转换 

分 类 号：TP314[自动化与计算机技术—计算机软件与理论] TN332[自动化与计算机技术—计算机科学与技术]