ARINC659芯片设计与实现关键技术研究  

Key Technology Research of ARINC659 Chip Design and Implementation

作　　者：许宏杰[1] 田泽[1] 郭亮[1] 刘宁宁[1] 王泉[1] 

机构地区：[1]中航工业西安航空计算技术研究所,陕西西安710068

出　　处：《计算机技术与发展》2014年第3期26-30,共5页Computer Technology and Development

基　　金："十二五"微电子预研(51308010601);总装预研基金(9140A08010712HK61095);中国航空工业集团公司创新基金(2010BD63111)

摘　　要：ARINC659总线是一个半双工传输的、总线交叉检验的、线性多点的串行容错总线,用于综合模块化航空电子系统机架内部各个在线可更换模块之间的通信,其总线传输时间和存储空间上具有高可靠性和高完整性等特点。在国外,该总线已广泛应用在航空、航天等领域。文中对ARINC659总线进行了概述,分析了ARINC659总线协议的关键技术,重点阐述了ARINC659芯片的体系架构设计、详细设计与实现、虚拟仿真验证及FPGA原型验证等关键技术。目前,ARINC659芯片已经一次流片成功,并成功应用在多个领域。ARINC659 bus is a linear,multi-drop communications medium which transfers half duplex serial data,and used for transferring digital data between line replaceable modules within integrated modular avionics. It has high-reliability and high-integrity in bus trans-mission time and the memory space. The bus has been widely used in aviation,aerospace and other fields in foreign country. Summarize ARINC659 bus,analyze the key techniques of ARINC659 bus protocol,expound the chip architecture,detail design and implementation, simulation verification,and FPGA verification of ARINC659 chip. At present,ARINC659 chip has already been successfully taped-out once and used in many fields.

关 键 词：ARINC659总线 同步 容错 验证 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]