超前进位加法器的优化设计  

Optimized Design on Carry Look-ahead Adder

作　　者：袁浩[1] 唐建[1] 方毅[2] 

机构地区：[1]中国科学技术大学电子科学与技术系,安徽合肥230027 [2]中国科学技术大学信息科学实验中心,安徽合肥230027

出　　处：《通信技术》2014年第3期339-342,共4页Communications Technology

摘　　要：在对超前加法器逻辑算法分析的基础上,介绍了一种优化设计方法。宽位加法器采用多层CLA(Carry Look-ahead Adder)块技术,按四位为一组进行组间超前进位,减小硬件延时,达到并行、高速的目的。并在晶体管级重点对全加器进行优化设计,从而降低整个电路的延时、面积和功耗。仿真结果表明,在SMIC65nm工艺下,设计出的16位超前进位加法器,其延时,面积,功耗相比传统结构都有了明显的改善,达到了优化的效果。This paper introduces a novel design method based on the analysis of CLA（ Carry Look-ahead） logic algorithm. The wide adder adopts the multilayer CLA block technique between groups,with four bits as a group,to reduce the hardware delay and achieve the parallel and high-speed purpose. The key point is to optimize the design of full adder at the transistor level,and thus to reduce the circuit delay, area and power consumption. Simulation result indicates that compared with the traditional structure, the delay, area and power consumption of the 16 bit CLA could be significantly improved,and the optimized effect in the environment of SMIC65nm thus be achieved.

关 键 词：超前进位 分层 加法器 优化 

分 类 号：TN432[电子电信—微电子学与固体电子学]