三阶PLL无源环路滤波器的设计与仿真  

Design and Simulation of Passive Loop Filter of Third-order PLL

作　　者：任青莲[1] 高文华[1] 郭萍[1] 

机构地区：[1]太原科技大学电子信息工程学院,太原030024

出　　处：《四川兵工学报》2014年第2期101-104,共4页Journal of Sichuan Ordnance

基　　金：2011年山西省高等学校教学改革项目;电工电子现代实验教学体系的研究与实践(J2011067)

摘　　要：为提高锁相环的性能,简化高阶锁相环中无源环路滤波器的设计过程,提出了三阶PLL中无源超前-滞后滤波器的一种设计方法。首先给出锁定状态锁相环的数学模型,选定使PLL特性稳定的无源滤波器的电路结构,根据结构求出锁相环的相位传递函数,确定使系统稳定的相位最大返回处频率,合理分配滤波器的零、极点,进而综合出环路滤波器的设计方法,以及电路中各元件的计算公式。给出了设计实例并进行了PSPICE仿真,结果表明其性能完全能达到设计要求。该方法对任意三阶PLL无源滤波器的设计都是实用的。In order to improve PLL performance and simplify passive loop filter design in high-order PLL, a design method is presented. First, we gave the mathematical model of PLL lock status, selected circuit of passive filter, and calculated the phase transfer function of PLL. Second, we determined the frequency of phase maximum return to make the system stable, allocated the poles and zeros of filters, and then synthe- sized the design method of filter and the formula of circuit component. A design example is given, and its frequency response is simulated based on Pspice. The results show that the performance can completely meet the design requirements. The method is practical for arbitrary three-order PLL passive loop filter.

关 键 词：PLL 超前-滞后滤波器 相位稳定裕度 PSPICE 

分 类 号：TN713.1[电子电信—电路与系统]